Timing in a VLSI tester can be generated in several ways. Some systems employ centrally located generators that provide a small number of timing references or edges that are distributed to test electronics on a shared basis. This provides a savings in hardware cost at the expense of programming flexibility. Others have separate and complete timing generators for each edge needed by every pin. This requires more hardware but it allows the system programmer to have the most flexibility in writing a device test program. In a timing system using shared address generator(s) to provide an address to shallow memories behind the timing reference generators, the tradeoff between totally shared resources and complete independence is balanced to allow at least a 50% reduction in the cost of the timing system without restricting the basic flexibility of a "TIMING PER PIN ARCHITECTURE".
VLSI test systems generally fall in two categories. One category is "SHARED RESOURCE" in which a small number of timing generators are distributed to the test pins on a shared basis. The second category is "PER PIN ARCHITECTURE" that duplicates timing generation circuitry for each pin. Both of these categories generally use counter circuits to generate sychronous course delays and various type of vernier circuits to generate finer delays. The main difference between the "shared resource" and the "per pin" systems with regard to timing generators is the number of counters and verniers required.
In a conventional VLSI tester with timing generators available on per pin basis, every generator uses a binary counter to count the number of clock cycles between the time zero reference and the carry signal that triggers a vernier, or finer delay circuit. If the timing can change "ON THE FLY" (from test pattern to test pattern as a functional test is executed), then each counter will require memory behind it to dictate what the digital count will be for that edge on that cycle. This combination of memory and counter behind every edge can result in a large amount of circuitry in systems with many pins and several edges per pin. This translates into large, costly machines to test VLSI parts, and directly impacts the test cost and hence the profitability of manufacturing the parts.
Other systems use a counter to directly address the memory that generates the edge. This scheme requires a very deep memory behind every edge due to the need for memory locations that correspond to each fundamental clock cycle that will occur between consecutive time zero markers. This is generally practical only when a small number of timing edges are provided (as in a shared resource architecture).